1. Field of the Invention
The present invention relates to a design method of a semiconductor integrated circuit, and a computer readable medium, and more particularly, to a design method of a semiconductor integrated circuit and a computer readable medium that optimize the layout of the semiconductor integrated circuit.
2. Description of Related Art
There has been an increasing demand for an increase in a speed of a semiconductor integrated circuit including a system on chip (SoC) due to an increase in a speed of systems mounted thereon and an increase in a macro size as a result of complicated functions. To meet this demand, a logic synthesis method and an arrangement/wiring design method using various high-speed circuit technologies have been developed.
An increase in functional macros in a semiconductor integrated circuit results in an increase in a size of the semiconductor integrated circuit and an increase in the length of a signal wiring passing through the functional macros, which increases the wiring delay. Thus, it becomes difficult to achieve high-speed operation in the semiconductor integrated circuit. One method that is typically used to reduce the influence of wiring capacitance components caused due to the increase in the length of the signal wiring is to insert a buffer logic cell that is able to be sufficiently driven and inverter logic cells formed of even number of stages (hereinafter referred to as repeaters) into the semiconductor integrated circuit, so as to reduce the wiring delay. In this case, a certain time is required to correct bypass wiring in order to change the repeater arrangement position. Thus, an efficient operation is required.
Japanese Unexamined Patent Application Publication No. 2006-65669 discloses a technique related to an automatic-arrangement-wiring apparatus in which layout design can be performed at an appropriate timing by one automatic-arrangement-wiring. The automatic-arrangement-wiring apparatus according to Japanese Unexamined Patent Application Publication No. 2006-65669 calculates the wiring length between functional macro cells or blocks using an existing technique such as a Manhattan distance, selects a wiring layer used according to the transfer rate required from the correlation between the transfer rate and the wiring length that are obtained, and inserts repeaters when the transfer rate does not satisfy the required value even when this wiring layer is used.
FIG. 13 is a block diagram showing a configuration of the automatic-arrangement-wiring apparatus according to Japanese Unexamined Patent Application Publication No. 2006-65669. As shown in FIG. 13, the automatic-arrangement-wiring apparatus according to Japanese Unexamined Patent Application Publication No. 2006-65669 includes a transfer rate and repeater-to-repeater distance determining unit 112, an arrangement processing unit 113, a wire-length estimating unit 114, a wire-length determining unit 115, a transfer rate calculating unit 116, a wiring layer assigning unit 117, a repeater inserting unit 118, a wiring processing unit 119, a timing verifying unit 120, and a drawing unit 121.
The transfer rate and repeater-to-repeater distance determining unit 112 acquires a relationship between a repeater-to-repeater distance and a transfer rate for each of a plurality of wiring layers having different time constants based on a relationship between the repeater-to-repeater distance and a delay time which is prepared beforehand for each of the plurality of wiring layers, and calculates the highest transfer rate for each of the plurality of wiring layers. Note that the transfer rate is the time required for signals to propagate over a unit length of the wiring layer connecting repeaters, and is therefore expressed in units of time per unit length. In accordance with the related art, high transfer rate indicates that the time required for signals to propagate over a unit distance of the wiring layer is short, whereas low transfer rate indicates long transfer time.
The delay time is the time required for signals to propagate between repeaters in the wiring layer, and the repeater-to-repeater distance is the wiring length between the repeaters in the wiring layer. In accordance with Japanese Unexamined Patent Application Publication No. 2006-65669, each delay of the repeaters is disregarded and the result of division of the delay time by the repeater-to-repeater distance is acquired as the transfer rate associated with this repeater-to-repeater distance.
FIG. 14 is a flow chart showing an operation of the automatic-arrangement-wiring apparatus according to Japanese Unexamined Patent Application Publication No. 2006-65669. The related art will be described with reference to this flow chart. First, before carrying out layout wiring, the transfer rate and repeater-to-repeater distance determining unit 112 reads electronic data stored in a hard disk device in advance indicating a relationship between the delay time and the repeater-to-repeater distance for each of a plurality of wiring layers to a RAM. The transfer rate and repeater-to-repeater distance determining unit 112 then calculates a transfer rate for each of the plurality of wiring layers from the relationship between the repeater-to-repeater distance and the delay time indicated by the electronic data, and acquires a relationship between the repeater-to-repeater distance and the transfer rate for each of the plurality of wiring layers. Then, the transfer rate and repeater-to-repeater distance determining unit 112 calculates the highest transfer rate for each of the plurality of wiring layers having different time constants from the relationship between the repeater-to-repeater distance and the transfer rate of each of the plurality of wiring layers. The above processing corresponds to step S101 shown in FIG. 14.
The arrangement processing unit 113 then carries out arrangement of blocks and macro cells using a netlist which defines a connection relationship among blocks and macro cells in each desired logical circuit (step S102 in FIG. 14). One of various types of known arrangement technologies can be used as this arrangement technique.
When the arrangement of blocks and macro cells is completed, the wire-length estimating unit 114 estimates the wiring length of each of wiring routes which are to be provided among the blocks and macro cells based on the results of the arrangement (step S103 in FIG. 14). Using a known technology such as a Manhattan distance or the like as a method of estimating the wiring length, the wire-length estimating unit 114 estimates the wiring length of each of the wiring routes (hereinafter referred to as estimated wiring length as appropriate) in consideration of the congestion degree and degree of difficulty of wiring according to the arrangement results.
When accepting information about the estimated wiring length from the wire-length estimating unit 114, the wire-length determining unit 115 compares this information about the estimated wiring length with information about the wiring length specified by a user, and determines whether or not the estimated wiring length is equal to or longer than the wiring length specified by the user (step S104 in FIG. 14). The wiring length specified by the user is a threshold of a wiring length which provides a maximum permissible delay time according to the specifications of the circuit design. The information of the wiring length specified by the user is input into the automatic-arrangement-wiring apparatus using an input device, e.g., a keyboard or a mouse.
In step S104 in FIG. 14, when the wiring length estimated by the wire-length estimating unit 114 is shorter than the wiring length specified by the user, the process shifts to wiring processing of step S108 in FIG. 14. On the other hand, when determining that the estimated wiring length is equal to or longer than the wiring length specified by the user, the wire-length estimating unit 114 outputs the fact that the estimated wiring length is equal to or longer than the wiring length specified by the user and the information about the estimated wiring length to the transfer rate calculating unit 116. The transfer rate calculating unit 116 then estimates a delay time which is required based on a timing value in the wiring length of each wiring route specified by the user to calculate a transfer rate (step S105 in FIG. 14).
The timing value specified by the user and provided to the wiring length of each wiring route is a timing limitation value for the wiring length of each wiring route in question which the user has specified according to the specifications of the circuit design. For example, the timing value can be a real wire capacitance. The timing value is input to the automatic-arrangement-wiring apparatus by using an input device, e.g., a keyboard or a mouse. The information about the transfer rate and delay time which are determined for the estimated wiring length of each wiring route which is determined to be equal to or longer than the wiring length specified by the user is output from the transfer rate calculating unit 116 to the wiring layer assigning unit 117.
The wiring layer assigning unit 117 then compares the transfer rate calculated by the transfer rate calculating unit 116 with the highest transfer rates each of which being predetermined for the plurality of wiring layers having different time constants, and selects and assigns a wiring layer having the lowest transfer rate from among wiring layers extracted in an area that does not exceed the transfer rate calculated by the transfer rate calculating unit 116 to each wiring route in question (step S106 in FIG. 14).
The repeater inserting unit 118 then uses the relationship between the repeater-to-repeater distance and the transfer rate which is predetermined by the transfer rate and repeater-to-repeater distance determining unit 112, so as to determine a repeater-to-repeater distance which minimizes the transfer rate of the wiring layer which is assigned to each wiring route in question by the wiring layer assigning unit 117. The repeater inserting unit 118 further compares the wiring length of the wiring layer with the repeater-to-repeater distance determined as mentioned above, and, when the wiring length of the wiring layer in question is longer than the determined repeater-to-repeater distance, inserts one or more repeaters, such as buffers, into each wiring route in question formed of the assigned wiring layer at intervals specified by the repeater-to-repeater distance (step S107 in FIG. 14).
When the wire-length determining unit 115, in step S104 in FIG. 14, determines that the estimated wiring length is shorter than the wiring length specified by the user, or when the processing up to above-mentioned step S107 in FIG. 14 is completed, the wiring processing unit 119 performs wiring processing on each of the plurality of wiring routes having an estimated wiring length, and also performs wiring processing on the wiring layer which is assigned to each wiring route by the wiring layer assigning unit 117 (in step S108 in FIG. 14). At this time, the automatic arrangement wiring apparatus performs this processing on the plurality of wiring routes in an increasing order of transfer rates required of wiring layers which are assigned to the plurality of wiring routes. As a result, wiring can be sequentially performed on the wiring layers in order of decreasing time constant and hence increasing transfer rate, but decreasing number of wiring resources. Thus, a fine wiring layer is wired first with the largest time constant and hence the lowest transfer rate, but the largest number of wiring resources. Therefore, automatic wiring with good efficiency in consideration of the wiring resources can be implemented.
The timing verifying unit 120 then performs timing verification on the automatically-arranged wiring layout which is thus obtained as mentioned above (in step S109 in FIG. 14), and determines whether timing error parts exist in the automatically-arranged wiring layout (in step S110 in FIG. 14). When determining that timing error parts exist in the automatically-arranged wiring layout, the process returns to step S106 in FIG. 14 in which it carries out the assignment of wiring layers to the plurality of wiring routes again.
For example, the wiring layer assigning unit 117 assigns a wiring layer having the second lowest transfer rate, which is selected from among wiring layers whose transfer rates do not exceed the transfer rate calculated by the transfer rate calculating unit 116 based on the relationship between the plurality of wiring layers and their lowest transfer rates, to each of the plurality of wiring routes. Then, wiring is sequentially performed on the wiring layers in order of decreasing time constant and hence increasing transfer rate, and decreasing number of wiring resources. Thus, a fine wiring layer is wired first. On the other hand, when determining that no timing error part exists in the automatically-arranged wiring layout, the timing verifying unit 120 notifies the drawing unit 121 of the fact. As a result, the drawing unit 121 displays the semiconductor layout created as mentioned above on a display screen of a computer device to provide it for a user.
In accordance with the automatic-arrangement-wiring apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2006-65669, when acquiring the relationship between the repeater-to-repeater distance and the transfer rate for each of the plurality of wiring layers, the transfer rate and repeater-to-repeater distance determining unit 112 can provide an amount of displacement which serves as an arrangement margin from ideal positions which are determined beforehand in consideration of the fact that repeaters cannot be actually arranged at the ideal positions (step S101 in FIG. 14). As a result, when it is impossible to arrange them at the ideal positions when repeaters are actually arranged, the positions where they are to be arranged can be adjusted according to this amount of displacement.
For a certain wiring route to which a wiring layer is assigned, even if it is determined that the transfer rate is the highest in a repeater-to-repeater distance, there is a case where repeaters cannot be arranged at the ideal positions specified by the repeater-to-repeater distance in terms of the arrangement space. In this case, the transfer rate and repeater-to-repeater distance determining unit 112 can receive a user-specified amount of displacement via a graphic display device or the like, and add the user-specified amount of displacement input by the user to the above-mentioned repeater-to-repeater distance. In this case, since the delay time increases by only a time corresponding to the increase in the repeater-to-repeater distance from the ideal one, the automatic-arrangement-wiring apparatus selects a wiring layer having a shorter transfer rate according to the increase in the repeater-to-repeater distance from the ideal one. For example, the wire-length estimating unit 114 estimates the wiring length of each of the plurality of wiring routes again in consideration of the amount of displacement from the ideal positions, or the wiring layer assigning unit 117 can change the assignment of a wiring layer to each of the plurality of wiring routes.